This invention relates to a gate pad protection structure and a manufacturing method therefor, and more particular to a gate pad protection structure for a power semiconductor device and a manufacturing method therefor.
Conventionally, the power semiconductor devices, e.g., MOSFET (Motel-Oxide-Semiconductor Field-Effect Transistor), IGBT (Isolated Gate Bipolar Transistor), or any other power semiconductor device having a gate pad structure, etc., generally has a gate pad protection structure for protecting and also avoiding the gate oxide layer being broken by the electric stress. Please refer to FIG. 1, it illustrates the schematic view of the gate pad protection structure of a power semiconductor device according to the prior art. As shown in FIG. 1, a thin gate oxide layer 11 is first formed on a silicon substrate 10. Then, a polysilicon layer 12 is formed on the thin gate oxide layer 11 by a deposition. Sequentially, a photolithographic and an etching processes are executed on the polysilicon layer 12 of an active area to form a polysilicon window 1101. Then, ion implantations are executed to form well area 101, source area 102 and shallow junction area 103 on the silicon substrate 10. Continuously, a dielectric layer 13 is formed on the polysilicon layer 12, and then a portion of the dielectric layer 13 is removed by a photolithographic and an etching processes. Finally, a metal layer 14 as shown in FIG. 1 is formed on the dielectric layer 13 to form a gate pad structure 15. However, when the conventional power semiconductor device is applied a high voltage, the gate pad structure described above should be protected to avoid the gate oxide layer being broken by the high electric stress. The conventional protecting method is to form a deep junction 104 directly under the gate pad structure and thus forms a p-n junction on the silicon substrate 10. This method will obviously reduce the field stresses of the surface of the silicon substrate and the area of the gate oxide layer. But this conventional method needs to increase a step of photo mask for forming the deep junction 104 in the process, especially for low voltage power semiconductor devices.
It is obviously known that how to provide an effective gate pad protection structure and to avoid the persecution of increasing one more step is a significant developing direction for the present invention. Thus, because of the technical defects described above, the applicant keeps on carving unflaggingly to develop a xe2x80x9cgate pad protection structure for power semiconductor device and manufacturing method thereforxe2x80x9d through wholehearted experience and research.
It is an object of the present invention to provide a gate pad protection structure for a power semiconductor device and a manufacturing method therefore for protecting and avoiding the gate oxide layer being broken by the electric stress.
It is another object of the present invention to provide a gate pad protection structure and a method therefor by forming a polysilicon window array on a polysilicon layer of an inactive area.
In accordance with an aspect of the present invention, a method for manufacturing a gate pad protection structure applied in a power semiconductor device, includes steps of (a) forming a gate oxide layer on a substrate, (b) forming a polysilicon layer on the gate oxide layer, (c) forming a polysilicon window and a polysilicon window array on the polysilicon layer, and (d) performing ion implantations via the polysilicon window and the polysilicon window array.
Preferably, the substrate is made of silicon.
Preferably, the power semiconductor device is one of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and IGBT (Isolated-Gate-Bipolar-Transistor) and any other power devices with gate-pad structures.
Preferably, the step (b) is executed by a chemical deposition.
Preferably, the step (c) is executed by a photolithographic and an etching processes.
Preferably, the step (d) further includes steps of (d1) forming a dielectric layer on the polysilicon layer and removing the dielectric layer over the polysilicon window, and (d2) forming a metal layer on the dielectric layer to form the gate pad protection structure.
Certainly, the step (d1) can be executed by a photolithographic and an etching processes.
Preferably, the step (d) is executed by a photo mask and ion implantations to form the field implantation area on the substrate corresponding to the polysilicon window and form the field implantation area cell array on the substrate corresponding to the polysilicon window array.
Certainly, the field implantation area cell array has plural field implantation area cells each of which is partially overlapped with a respective adjacent one to make an electrical short circuit and a ground connection.
Certainly, each of plural field implantation area cells substantially has an identical structure to that of the field implantation area.
In accordance with another aspect of the present invention, a gate pad protection structure for a power semiconductor device, includes a substrate, a field implantation area disposed in the substrate, a field implantation area cell array disposed in the substrate and having plural field implantation area cells each of which substantially has an identical structure to that of the field implantation area, wherein the field implantation area cell array and the field implantation area are simultaneously formed in the substrate, and a gate pad structure having a polysilicon window and a polysilicon window array formed on the substrate for protecting the gate pad structure by the field implantation area cell array.
Prefersbly, the substrate is made of silicon.
Prefersbly, the power semiconductor device is one of MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) and IGBT (Isolated-Gate-Bipolar-Transistor) and any other power devices with gate-pad structures.
Certainly, each of plural field implantation area cells can be overlapped with a respective adjacent one to make an electrical short circuit and a ground connection.
The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed descriptions and accompanying drawings, in which: